1. Field of the Invention
This invention relates generally to a dynamic random access memory device, and in particular to a dynamic random access memory device capable of performing a self-controlled periodic refresh cycle of operation.
2. Description of the Prior Art
Conventionally static random access memories or SRAMs have been used as battery backed-up memories in personal computers. In recent years, however, it has been proposed to employ dynamic random access memories or DRAMs because the DRAM has a higher storage capacity than the SRAM. For this purpose, it is desired that the DRAM dissipates a smallest possible amount of current while not being addressed in a data holding state.
In order to have a brief background understanding on the field of technology to which this invention pertains, reference is made to FIG. 5, which illustrates in block diagram an overall arrangement of a prior-art DRAM. The DRAM includes an array 58 of memory cells for storing data signals; an address buffer 54 for receiving address signals which select memory cells; row and column decoders for decoding the address signals; and a sense amplifier 63 for reading the stored data signal from the memory cells and amplifying them. The DRAM also includes an input buffer 59 for receiving data signal and an output buffer 60 for supplying data signals, both of which are connected to the memory array 58 through an I/O gate 57.
The address buffer 54 is connected to receive externally applied address signals ext. A0-A9 or internally applied address signals Q0-Q8 generated by a refresh counter 53. The refresh counter 53 is regulated by a refresh controller 52 in response to RAS and CAS signals applied thereto through the clock generator 51. A V.sub.BL circuit 62 for generating bit line precharge voltage (hereinafter referred to as V.sub.BL) is connected to the memory array 58 via an equalizer circuit 61.
FIG. 6A shows the circuit configuration of a memory cell and its associated circuits in the prior-art DRAM. And FIG. 6B illustrates a timing diagram for the circuitry of FIG. 6A. This circuit arrangement is disclosed in Digest of Technical Papers for the 1985 International Solid-State Circuit Conference (ISSCC 85), pp. 252-253.
Referring to FIG. 6A, a memory cell M is shown connected between a bit line BLj and a word line WLi. The memory cell M comprises a capacitor Cs and an NMOS switching transistor Qs, while the sense amplifier 63 comprises a CMOS flip flop connected between the bit lines BLj and BLj. The CMOS flip flop includes PMOS transistors Q3 and Q4 and NMOS transistors Q1 and Q2, and it is connected between a supply voltage Vcc and a ground potential Vss via a PMOS transistor Q.sub.SP and and an NMOS transistor Q.sub.SN. The transistor Q.sub.SP and Q.sub.SN have their gates connected to receive sense trigger signals S.sub.P and S.sub.N, respectively. The equalizer circuit 61 comprises an NMOS transistor Q5 connected between the bit line BLj and BLj, and a pair of NMOS transistors Q6 and Q7 which series connected between the bit lines BLj and BLj. These transistors have their gates connected to receive an equalizer signal EQ.
The precharge voltage generator circuit 62 is connected via the NMOS transistor Q.sub.PR to a junction between the transistors Q6 and Q7 by an L.sub.BL line. The I/O gate 57 comprises an NMOS transistor Q8 coupled between the bit line BLj and an input-output line I/O, and an NMOS transistor Q9 coupled between the bit line BLj and an input-output line I/ . The transistors Q8 and Q9 have their gates connected to receive signals Yj from the column decoder. A signal generator circuit 69 is provided to generate various control signals PR, EQ, S.sub.P and S.sub.N which will be explained below.
Referring now to FIGS. 6A and 6B, the read-out and refresh operations of the DRAM are described.
In a read-out operation, first, the signal generating circuit 69 provides an equalizer signal EQ and a precharge signal PR, in response to which the transistors Q.sub.PR, Q5, Q6 and Q7 are turned on, and the bit lines BLj and BLj are brought to an equalize potential of V.sub.BL (usually Vcc/2). After the RAS signal falls to its low level, signals EQ and PR both shift to a low level. Then, the word line signal WLi rises to its high level to turn on the switching transistor Q.sub.S in the memory cell M. Upon receipt of a signal from the memory cell M, the potential on the bit line BLj undergoes a slight change, causing a small potential difference between the bit line BLj and the bit line BLj which is at Vcc/2.
Generally at this point, the signals S.sub.P and S.sub.N also undergo a change, driving the sense amplifier 63 into operation. Thus, the sense amplifier 63 amplifies the small potential difference between the bit lines BLj and BLj. An application of a high level signal Yj to the gates of the transistors Q8 and Q9 causes an amplified data signal to be transferred through the transistors Q8 and Q9 to the input-output line I/O.
It is pointed out here that in the refresh cycle of operation, the amplified data signal is not applied to the input-output line I/O. Instead, it is supplied back to the capacitor Cs through the bit line BLj in the memory cell M.
Referring to FIGS. 7A and 7B, there are illustrated circuit configurations of a prior-art V.sub.BL circuit for generating bit line precharge voltage. The circuit configuration of FIG. 7B is disclosed in USP No. 4,692,689issued to Takemae on Sept. 8, 1987 and entitled "FET Voltage Reference Circuit having Threshold Voltage Compensation".
As shown in FIG. 7A, the precharge voltage generator circuit 62 comprises resistors R5 and R6 which are series connected between the supply voltage Vcc and the ground potential Vss. A fixed level precharge voltage V.sub.BL is obtained at the junction between the resistors R5 and R6.
As shown in FIG. 7B, the generator circuit for the bit line precharge voltage V.sub.BL includes a first series-connection of resistors R1 and R2, NMOS transistors Q12 and Q13, all of which are series connected between the supply voltage Vcc and the ground potential Vss. The generator circuit also includes a second series-connection of PMOS transistors Q15 and Q16, resistors R3 and R4 which are similarly series connected between the supply voltage Vcc and the ground potential Vss. The output stage of the generator circuit comprises an NMOS transistor Q11 and a PMOS transistor Q14 of a third series connection between the supply voltage Vcc and the ground potential Vss. It is noted that the transistors Q12, Q13, Q15 and Q16 have their gates coupled to their respective drains. On the other hand, the transistor Q11 has its gate coupled to the junction between the resistors R1 and R2, while the transistor Q14 has its gate coupled to the junction between the resistors R3 and R4. With the circuit arrangement, the bit line precharging voltage V.sub.BL is provided at the junction point between the transistors Q11 and Q14.
As stated hereinabove, the memory cell for the DRAM usually has a capacitor of MOS structure for storing data representing charge, and the stored charge tends to be dissipated due to the charge leakage at the junction of the MOS type capacitor. In order to prevent the stored data-bearing charge from being lost, it is essential to periodically read out the stored data signals and write them back again after amplifying the read-out signals in a refresh cycle of operation.
As the refresh operation for the DRAM, the RAS only refresh and the CAS before RAS refresh are currently used in the industry. In the RAS only refresh, as in the normal read/write cycle of operation, row address signals are externally supplied to the DRAM during the RAS cycle. On the other hand, in the CAS before RAS refresh, the refresh cycle is initiated in response to the externally applied CAS before RAS signal, subsequent to which the refresh counter built in the DRAM sequentially generates row address signals under the control of RAS clock signals. The CAS before RAS refresh mode eliminates the need for externally supplied address signals, and it is called an auto-refresh mode.
In contrast to these refresh cycles performed under the control of externally supplied clock signals, the so-called self-refresh cycle operation has been proposed and put into actual use in the DRAM. In the self-refresh cycle, the timer and address counter built in the DRAM carry out the desired refresh operation automatically and on their own without the aid of clock signals supplied from the outside. This type of refresh operation is disclosed in an article entitled, "A 64Kbit MOS Dynamic RAM with Auto/Self Refresh Functions (the Journal of Electronics and Communications, January 1983, Vol. J66 -C, No. 1, pp. 103-110)".
In order to decrease the amount of electric current consumed in the DRAM during the self-refresh cycle, it is advisable to conduct the refresh operation at time intervals longer than those employed in the conventional refreshing procedures including the auto-refresh mentioned above. For example, in the case of a 1 M bit DRAM, it is a common practice to perform 512 refresh cycles at a time interval of 8 ms between cycles. If the timer is set to provide an interval of 16 ms between refresh cycles, then the current consumption would be considerably reduced. A rough estimate is now made assuming that the DRAM is normally supplied with an electric current Icc of about 100 .mu.A and it consumes about 30 mA/220ns during every refresh cycle, then 550 .mu.A is used up during 512 refresh cycles with a 8 ms inter-cycle interval, and 330.mu.A during 512 refresh cycles with a 16 ms inter-cycle interval. In short, the current consumption could be saved by some 40% when the refresh cycle is repeated at an interval of 16 ms.
In this manner, the current consumption is considerably reduced if the refresh interval in the self-refresh cycles is set longer than that in the normal refresh cycles. However, it gives rise to a problem that the sense margin in reading out of the signal stored in the memory cell becomes smaller.
Referring to FIG. 8, there is illustrated relations between the bit line potential (electron potential) and the potential on the capacitor in the memory cell. As shown in FIG. 6A, in the N-type memory cell M, a voltage V.sub.H at the storage node Cs of a capacitor which holds a "H" level data signal is at the level of the supply voltage Vcc right after the data signal has been written into the memory cell M. However, due to the charge leakage at the junction between the capacitor Cs and the P-channel substrate of the DRAM, electrons (indicated by a hatched portion) are transferred from the substrate to the capacitor, resulting in an gradual decrease of the potential at the node Ns down to V.sub.H. On the other hand, the bit line pair BLj and BLj between which the memory cell M is connected is precharged to 1/2Vcc. A potential change .DELTA.V.sub.SH1 on the bit line BLj when the voltage held in the capacitor Cs is applied to the bit line under the condition is expressed as follows: EQU .DELTA.V.sub.SH1 = (V.sub.H - Vcc/2) .times.Cs (C.sub.B +Cs) (1)
where Cs: a capacitance of capacitor Cs
C.sub.B : a capacitance of bit line BLj
When an "L"level data signal is written into the capacitor Cs of the memory cell M, the node Ns is brought into an electron-saturated state where the potential at the node is 0 volts. This potential does not change as time passes because electrons are being continuously supplied. Thus, a potential change .DELTA.V.sub.SL on the bit line which is brought about by the application of the "L"level data signal from the capacitor Cs to the bit line BLj is given as: EQU .DELTA.V.sub.SL =(Vcc/2).times.Cs/(C.sub.B +Cs) (2)
The potential change on the bit line BLj when the "H" level data signal is applied is smaller than that when the "L" level data signal is applied as expressed by the following equation: EQU .DELTA.V.sub.SL - .DELTA.V.sub.SH1 .times.(Vcc -V.sub.H .times.Cs/(C.sub.B +Cs) (3)
This means that the sensing margin for reading out the data signal falls from Vcc/2 to Vm2 due to the potential change on the node Ns from Vcc to V.sub.H.
In view of the above described fact that the potential at the storage node Ns of the capacitor C.sub.B gradually decreases after the "H" level data signal has been written into the capacitor, setting the interval between refreshing cycles longer tends to adversely affect the reliable data storage of the DRAM.